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ultrafast, 4 ns single-supply comparators ad8611/ad8612 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features 4 ns propagation delay at 5 v single-supply operation: 3 v to 5 v 100 mhz input latch function applications high speed timing clock recovery and clock distribution line receivers digital communications phase detectors high speed sampling read channel detection pcmcia cards zero-crossing detector high speed analog-to-digital converter (adc) upgrade for lt1394 and lt1016 designs pin configurations v+ in+ v? in? qa qa gnd latch 1 2 3 4 8 7 6 5 ad8611 top view (not to scale) 06010-001 figure 1. 8-lead narrow body soic (r-8) qa v+ 1 in+ 2 in? 3 v? 4 8 qa 7 gnd 6 latch 5 ad8611 top view (not to scale) 06010-002 figure 2. 8-lead msop (rm-8) gnd lea v? ina? ina + gnd leb v+ inb? inb+ qa qa qb q b 1 2 3 4 5 6 7 ad8612 14 13 12 11 10 9 8 top view (not to scale) 06010-003 figure 3. 14-lead tssop (ru-14) general description the ad8611/ad8612 are single and dual 4 ns comparators with latch function and complementary output. the latch is not functional if v cc is less than 4.3 v. fast 4 ns propagation delay makes the ad8611/ad8612 good choices for timing circuits and line receivers. propagation delays for rising and falling signals are closely matched and tracked over temperature. this matched delay makes the ad8611/ad8612 good choices for clock recovery because the duty cycle of the output matches the duty cycle of the input. the ad8611 has the same pinout as the lt1016 and lt1394, with lower supply current and a wider common-mode input range, which includes the negative supply rail. the ad8611/ad8612 are specified over the industrial temper- ature range (?40c to +85c). the ad8611 is available in both 8-lead msop and narrow 8-lead soic surface-mount packages. the ad8612 is available in a 14-lead tssop surface-mount package.
ad8611/ad8612 rev. a | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 pin configurations ........................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 thermal resistance ...................................................................... 5 esd caution.................................................................................. 5 pin configurations and function descriptions ........................... 6 typical performance characteristics ............................................. 7 applications..................................................................................... 10 optimizing high speed performance ..................................... 10 upgrading the lt1394 and lt1016......................................... 10 maximum input frequency and overdrive............................ 10 output loading considerations............................................... 11 using the latch to maintain a constant output.................... 11 input stage and bias currents .................................................. 11 using hysteresis ......................................................................... 11 clock timing recovery............................................................. 12 a 5 v, high speed window comparator................................ 12 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 17 revision history 8/06rev. 0 to rev. a updated format..................................................................universal added no latch if v cc < 4.3 v .........................................universal changes to pin names .......................................................universal added pin configurations and function descriptions page ..... 6 changes to table 8.......................................................................... 12 changes to figure 26...................................................................... 12 changes to ordering guide .......................................................... 17 4/00revision 0: initial version
ad8611/ad8612 rev. a | page 3 of 20 specifications v+ = 5.0 v, v? = v gnd = 0 v, t a = 25c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit input characteristics offset voltage v os 1 7 mv ?40c t a +85c 8 mv offset voltage drift v os /t 4 v/c input bias current i b v cm = 0 v C6 C4 a i b ?40c t a +85c C7 C4.5 a input offset current i os v cm = 0 v 4 a input common-mode voltage range v cm 0.0 3.0 v common-mode rejection ratio cmrr 0 v v cm 3.0 v 55 85 db large signal voltage gain a vo r l = 10 k 3000 v/v input capacitance c in 3.0 pf latch enable input logic 1 voltage threshold v ih v cc > 4.3 v 2.0 1.65 v logic 0 voltage threshold v il v cc > 4.3 v 1.60 0.8 v logic 1 current i ih v cc > 4.3 v, v lh = 3.0 v C1.0 C0.3 a logic 0 current i il v cc > 4.3 v, v ll = 0.3 v C5 C2.7 a latch enable pulse width t pw(e) v cc > 4.3 v 3 ns setup time t s v cc > 4.3 v 0.5 ns hold time t h v cc > 4.3 v 0.5 ns digital outputs logic 1 voltage v oh i oh = 50 a, v in > 250 mv 3.0 3.35 v logic 1 voltage v oh i oh = 3.2 ma, v in > 250 mv 2.4 3.4 v logic 0 voltage v ol i ol = 3.2 ma, v in > 250 mv 0.25 0.4 v dynamic performance input frequency f max 400 mv p-p sine wave 100 mhz propagation delay t p 200 mv step with 100 mv overdrive 1 4.0 5.5 ns ?40c t a +85c 5 ns propagation delay t p 100 mv step with 5 mv overdrive 5 ns differential propagation delay (rising propagation delay vs. falling propagation delay) t p 100 mv step with 100 mv overdrive 1 0.5 2.0 ns rise time 20% to 80% 2.5 ns fall time 80% to 20% 1.1 ns power supply power supply rejection ratio psrr 4.5 v v+ 5.5 v 55 73 db v+ supply current 2 i+ 5.7 10 ma ?40c t a +85c 10 ground supply current 2 i gnd v o = 0 v, r l = 3.5 7 ma ?40c t a +85c 7 ma v? supply current 2 i? 2.2 4 ma ?40c t a +85c 5 ma 1 guaranteed by design. 2 per comparator.
ad8611/ad8612 rev. a | page 4 of 20 v+ = 3.0 v, v? = vgnd = 0 v, t a = 25c, unless otherwise noted. table 2. parameter symbol conditions min typ max unit input characteristics offset voltage v os 1 7 mv input bias current i b v cm = 0 v ?6 ?4.0 a i b ?40c t a +85c ?7 ?4.5 a input common-mode voltage range v cm 0 1.0 v common-mode rejection ratio cmrr 0 v v cm 1.0 v 55 db output characteristics output high voltage v oh i oh = ?3.2 ma, v in > 250 mv 1.2 1 v output low voltage v ol i ol = +3.2 ma, v in > 250 mv 0.3 v latch enable input not functional if v cc < 4.3 v power supply power supply rejection ratio psrr 2.7 v v+ 6 v 46 db supply currents v o = 0 v, r l = v+ supply current 2 i+ ?40c t a +85c 4.5 6.5 ma 10 ma ground supply current 2 i gnd ?40c t a +85c 2.5 3.5 ma 5.5 ma vC supply current 2 i? 2 3.5 ma ?40c t a +85c 4.8 ma dynamic performance propagation delay t p 100 mv step with 20 mv overdrive 3 4.5 6.5 ns 1 output high voltage without pull-up resistor. it may be useful to have a pull-up resistor to v+ for 3 v operation. 2 per comparator. 3 guaranteed by design.
ad8611/ad8612 rev. a | page 5 of 20 absolute maximum ratings table 3. parameter rating total analog supply voltage 7.0 v digital supply voltage 7.0 v input voltage 1 4 v differential input voltage 5 v output short-circuit duration to gnd indefinite storage temperature range r, ru, rm packages ?65c to +150c operating temperature range ?40c to +85c junction temperature range r, ru, rm packages ?65c to +150c lead temperature range (soldering, 10 sec) 300c 1 the analog input voltage is equal to 4 v or the analog supply voltage, whichever is less. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance table 4. package type ja 1 jc unit 8-lead soic (r) 158 43 c/w 8-lead msop (rm) 240 43 c/w 14-lead tssop (ru) 240 43 c/w 1 ja is specified for the worst-case conditio ns, that is, a device in socket for p-dip and a device soldered in circuit board for soic and tssop. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad8611/ad8612 rev. a | page 6 of 20 pin configurations and function descriptions v+ in+ v? in? qa qa gnd latch 1 2 3 4 8 7 6 5 ad8611 top view (not to scale) 06010-001 qa v+ 1 in+ 2 in? 3 v? 4 8 qa 7 gnd 6 latch 5 ad8611 top view (not to scale) 06010-002 gnd lea v? ina? ina + gnd leb v+ inb? inb+ qa qa qb q b 1 2 3 4 5 6 7 ad8612 14 13 12 11 10 9 8 top view (not to scale) 06010-003 figure 4. 8-lead narrow body soic pin configuration figure 5. 8-lead msop pin configuration figure 6. 14-lead tssop pin configu ration table 5. pin function descriptions pin o. soic and msop tssop mnemonic description 1 10 v+ positive supply terminal. 2 in+ noninverting analog input of the differential input stage. 3 in? inverting analog input of the differential input stage. 4 5 v? negative supply terminal. 5 latch latch enable input. 6 3, 12 gnd negative logic supply 7 1 qa one of two complementary output for channel a. 8 2 qa one of two complementary output for channel a. 14 qb one of two complementary output for channel b. 13 qb one of two complementary output for channel b. 4 lea channel a latch enable. 11 leb channel b latch enable. 7 ina+ noninverting analog input of th e differential input stage for channel a. 6 ina? inverting analog input of the differential input stage for channel a. 8 inb+ noninverting analog input of th e differential input stage for channel b. 9 inb? inverting analog input of the differential input stage for channel b.
ad8611/ad8612 rev. a | page 7 of 20 typical performance characteristics temperature (c) 8 0 ?50 100 ?25 propagation delay (ns) 0 25 50 75 6 5 4 2 1 3 7 v+ = 5v overdrive > 10mv pd? pd+ 06010-004 figure 7. propagation delay vs. temperature propagation delay (ns) overdrive (mv) 18 16 0 0 25 5 101520 10 6 4 2 14 12 8 v+ = 5v t a = 25c pd? pd+ 06010-005 figure 8. propagation delay vs. overdrive capacitance (pf) 8 0 0 80 20 40 60 6 5 4 2 1 3 7 propagation delay (ns) v+ = 5v t a = 25c overdrive > 10mv pd? pd+ 06010-006 figure 9. propagation delay vs. load capacitance propagation delay (ns) source resistance (k ? ) 18 0 02 0.5 1.0 6 2 14 12 8 . 5 pd? pd+ v+ = 5v t a = 25c overdrive = 5mv 1.5 2.0 0 6010-007 figure 10. propagation delay vs. source resistance propagation delay (ns) supply voltage (v) 8 7 0 6 23 45 4 3 2 1 6 5 pd? pd+ t a = 25c step = 100mv overdrive > 10mv 06010-008 figure 11. propagation delay vs. supply voltage common-mode voltage (v) 35 30 0 15 10 5 25 20 propagation delay (ns) t a = 25c step = 100mv overdrive = 50mv 6 23 45 pd? pd+ 06010-009 figure 12. propagation delay vs. common-mode voltage
ad8611/ad8612 rev. a | page 8 of 20 temperature (c) 1.2 0 ?60 100 ?40 v os (mv) ?20 0 20406080 1.0 0.8 0.6 0.4 0.2 v s = 3v v s = 5v 06010-010 figure 13. offset voltage vs. temperature input frequency (mhz) 40 35 0 100 11 0 i sy+ (ma) 30 25 5 20 15 10 v+ = 5v t a =25c 06010-011 figure 14. supply current vs. input frequency temperature (c) 2.0 0 ?50 100 ?25 timing (ns) 0 25 50 75 1.4 1.2 1.0 0.6 0.2 0.8 1.8 v+ = 5v setup time hold time 1.6 0.4 06010-012 figure 15. latch setup and hold time vs. temperature sink current (ma) 0.40 0 load current (v) 0.35 0.20 0.15 0.10 0.05 0.30 0.25 01 246810 2 +85c +25c ?40c +85c +25c ?40c 0 6010-013 figure 16. output low voltage vs. load current (sinking) over temperature load current (ma) 4.0 2.4 output high voltage (v) 3.8 3.2 3.0 2.8 2.6 3.6 3.4 0 12 246810 +25c +85c ?40c 06010-014 figure 17. output high voltage vs. load current (sourcing) over temperature temperature (c) 8 0 ?60 100 ?40 i sy (ma) ?20 0 20 40 60 80 7 5 4 2 1 3 6 v s = 3v v s = 5v 0 6010-015 figure 18. supply current vs. temperature
ad8611/ad8612 rev. a | page 9 of 20 temperature (c) 0 ?0.5 ?4.5 50 100 0 50 v s = 3v ?3.0 ?3.5 ?4.0 ?1.5 ?2.0 ?1.0 v s = 5v ?2.5 i gnd (ma) 06010-016 figure 19. i gnd vs. temperature temperature (c) 0 ?3.0 ?60 100 ?40 ?20 0 20406080 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 i sy (ma) v s = 3v v s = 5v 06010-017 figure 20. i sy ? vs. temperature time (2ns/div) 0v voltage v out v in ?v in trace @ 10mv/div v out trace @ 1v/div v+ = 5v t a = 25c 06010-018 figure 21. rising edge response time (2ns/div) 0v voltage ?v in trace @ 10mv/div v out trace @ 1v/div v in v out v+ = 5v t a = 25c 0 6010-019 figure 22. falling edge response time (4ns/div) 0v voltage v in v out ?v in trace @ 10mv/div v out trace @ 1v/div v+ = 5v t a = 25c 06010-020 figure 23. response to a 50 mhz, 100 mv input sine wave
ad8611/ad8612 rev. a | page 10 of 20 applications optimizing high speed performance as with any high speed comparator or amplifier, proper design and layout of the ad8611/ad8612 should be used to ensure optimal performance. excess stray capacitance or improper grounding can limit the maximum performance of high speed circuitry. minimizing resistance from the source to the comparators input is necessary to minimize the propagation delay of the circuit. source resistance in combination with the equivalent input capacitance of the ad8611/ad8612 creates an r-c filter that could cause a lagged voltage rise at the input to the comparator. the input capacitance of the ad8611/ad8612 in combination with stray capacitance from an input pin to ground results in several picofarads of equivalent capacitance. using a surface-mount package and a minimum of input trace length, this capacitance is typically around 3 pf to 5 pf. a combination of 3 k source resistance and 3 pf of input capacitance yields a time constant of 9 ns, which is slower than the 4 ns propagation delay of the ad8611/ad8612. source impedances should be less than 1 k for best performance. another important consideration is the proper use of power- supply-bypass capacitors around the comparator. a 1 f bypass capacitor should be placed within 0.5 inches of the device between each power supply pin and ground. another 10 nf ceramic capacitor should be placed as close as possible to the device in parallel with the 1 f bypass capacitor. the 1 f capacitor reduces any potential voltage ripples from the power supply, and the 10 nf capacitor acts as a charge reservoir for the comparator during high frequency switching. a continuous ground plane on the pc board is also recommended to maximize circuit performance. a ground plane can be created by using a continuous conductive plane over the surface of the circuit board, only allowing breaks in the plane for necessary traces and vias. the ground plane provides a low inductive current return path for the power supply, thus eliminating any potential differences at various ground points throughout the circuit board caused from ground bounce. a proper ground plane can also minimize the effects of stray capacitance on the circuit board. upgrading the lt1394 and lt1016 the ad8611 single comparator is pin-for-pin compatible with the lt1394 and lt1016 and offers an improvement in propagation delay over both comparators. these devices can easily be replaced with the higher performance ad8611; however, there are differ- ences, so it is useful to ensure that the system still operates properly. the five major differences between the ad8611 and the lt1016 include input voltage range, input bias currents, propagation delay, output voltage swing, and power consumption. input common-mode voltage is found by taking the average of the two voltages at the inputs to the comparator. the lt1016 has an input voltage range from 1.25 v above the negative supply to 1.5 v below the positive supply. the ad8611 input voltage range extends down to the negative supply voltage to within 2 v of v+. if the input common-mode voltage is exceeded, input signals should be shifted or attenuated to bring them into range, keeping in mind the note about source resistance in the optimizing high speed performance section. for example, an ad8611 powered from a 5 v single supply has its noninverting input connected to a 1 v peak-to-peak, high frequency signal centered around 2.3 v and its inverting input connected to a fixed 2.5 v reference voltage. the worst-case input common-mode voltage to the ad8611 is 2.65 v. this is well below the 3.0 v input common-mode voltage range to the comparator. note that signals much greater than 3.0 v result in increased input currents and may cause the comparator to operate more slowly. the input bias current to the ad8611 is 7 a maximum over temperature (?40c to +85c). this is identical to the maximum input bias current for the lt1394, and half of the maximum i b for the lt1016. input bias currents to the ad8611 and lt1394 flow out from the comparators inputs, as opposed to the lt1016 whose input bias current flows into its inputs. using low value resistors around the comparator and low impedance sources will minimize any potential voltage shifts due to bias currents. the ad8611 is able to swing within 200 mv of ground and within 1.5 v of positive supply voltage. this is slightly more output voltage swing than the lt1016. the ad8611 also uses less current than the lt10165 ma as compared to 25 ma of typical supply current. the ad8611 has a typical propagation delay of 4 ns, compared with the lt1394 and lt1016, whose propagation delays are typically 7 ns and 10 ns, respectively. maximum input frequency and overdrive the ad8611 can accurately compare input signals up to 100 mhz with less than 10 mv of overdrive. the level of overdrive required increases with ambient temperature, with up to 50 mv of overdrive recommended for a 100 mhz input signal and an ambient temperature of +85c. it is not recommend to use an input signal with a fundamental frequency above 100 mhz because the ad8611 could draw up to 20 ma of supply current and the outputs may not settle to a definite state. the device returns to its specified performance once the fundamental input frequency returns to below 100 mhz.
ad8611/ad8612 rev. a | page 11 of 20 output loading considerations the ad8611 can deliver up to 10 ma of output current without increasing its propagation delay. the outputs of the device should not be connected to more than 40 ttl input logic gates or drive less than 400 of load resistance. the ad8611 output has a typical output swing between ground and 1 v below the positive supply voltage. decreasing the output load resistance to ground lowers the maximum output voltage due to the increase in output current. table 6 shows the typical output high voltage vs. load resistance to ground. table 6. maximum output vo ltage vs. resistive load output load to ground v+ ? v out, hi (typ) 300 1.5 v 500 1.3 v 1 k 1.2 v 10 k 1.1 v >20 k 1.0 v connecting a 500 to 2 k pull-up resistor to v+ on the output helps increase the output voltage so that it is closer to the positive rail; in this configuration, however, the output voltage will not reach its maximum until 20 ns to 50 ns after the output voltage switches. this is due to the r-c time constant between the pull-up resistor and the output and load capacitances. the output pull-up resistor cannot improve propagation delay. the ad8611 is stable with all values of capacitive load; however, loading an output with greater than 30 pf increases the propagation delay of that channel. capacitive loads greater than 500 pf also create some ringing on the output wave. table 7 shows propagation delay vs. several values of load capacitance. the loading on one output of the ad8611 does not affect the propagation delay of the other output. table 7. propagation delay vs. capacitive load c l (pf) t pd rising (ns) t pd falling (ns) <10 3.5 3.5 33 5 5 100 8 7 390 14.5 10 680 26 15 using the latch to maintain a constant output with the v cc supply at a nominal 5 v, the latch input to the ad8611/ad8612 can be used to retain data at the output of the comparator. when the latch voltage goes high, the output voltage remains in its previous state, independent of changes in the input voltage. the setup time for the ad8611/ad8612 is 0.5 ns and the hold time is 0.5 ns. setup time is defined as the minimum amount of time the input voltage must remain in a valid state before the latch is activated for the latch to function properly. hold time is defined as the amount of time the input must remain constant after the latch voltage goes high for the output to remain latched to its voltage. the latch input is ttl and cmos compatible, so a logic high is a minimum of 2.0 v and a logic low is a maximum of 0.8 v. the latch circuitry in the ad8611/ad8612 has no built-in hysteresis. at or below approximately 4.1 v, the latch pin becomes unresponsive and should normally be tied low for low v cc operation. input stage and bias currents the ad8611 and ad8612 each use a bipolar pnp differential input stage. this enables the input common-mode voltage range to extend from within 2.0 v of the positive supply voltage to 200 mv below the negative supply voltage. therefore, using a single 5 v supply, the input common-mode voltage range is ?200 mv to +3.0 v. input common-mode voltage is the average of the voltages at the two inputs. for proper operation, the input common-mode voltage should be kept within the common- mode voltage range. the input bias current for the ad8611/ad8612 is 4 a, which is the amount of current that flows from each input of the comparator. this bias current goes to zero on an input that is high and doubles on an input that is low, which is a characteristic common to any bipolar comparator. care should be taken in choosing resistances to be connected around the comparator because large resistors could significantly decrease the voltage due to the input bias current. the input capacitance for the ad8611/ad8612 is typically 3 pf. this is measured by inserting a 5 k source resistance in series with the input and measuring the change in propagation delay. using hysteresis hysteresis can easily be added to a comparator through the addition of positive feedback. adding hysteresis to a comparator offers an advantage in noisy environments where it is undesirable for the output to toggle between states when the input signal is close to the switching threshold. figure 24 shows a simple method for configuring the ad8611 or ad8612 with hysteresis. v ref r1 signal comparato r r2 c f 0 6010-021 figure 24. configuring the ad8611/ad8612 with hysteresis in figure 24 , the input signal is connected directly to the inverting input of the comparator. the output is fed back to the noninverting input through r1 and r2. the ratio of r1 to r1 + r2 establishes the width of the hysteresis window, with v ref setting the center of the window, or the average switching voltage. the qa or qb output switches low when the input
ad8611/ad8612 rev. a | page 12 of 20 voltage is greater than v hi , and does not switch high again until the input voltage is less than v lo , as given in equation 1: () ref ref hi v rr r v v + + ?+= 21 1 5.1v (1) 21 2 rr r vv ref lo + = where v+ is the positive supply voltage. the capacitor c f is optional and can be added to introduce a pole into the feedback network. this has the effect of increasing the amount of hysteresis at high frequencies, which is useful when comparing relatively slow signals in high frequency noise environments. at frequencies greater than f p , the hysteresis window approaches v hi = v+ ? 1.5 v and v lo = 0 v. for frequencies less than f p , the threshold voltages remain as in equation 1. clock timing recovery comparators are often used in digital systems to recover clock timing signals. high speed square waves transmitted over any distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. a high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay. figure 25 shows v out vs. v in as the ad8611 is used to recover a 65 mhz, 100 mv peak-to-peak distorted clock signal into a 4 v peak-to-peak square wave. the lower trace is the input to the ad8611, and the upper trace is the qa or qb output from the comparator. the ad8611 is powered from a 5 v single supply. time (10ns/div) 2v/div v out v in 20mv/div 06010-022 figure 25. using the ad8611 to recover a noisy clock signal a 5 v, high speed window comparator a window comparator circuit is used to detect when a signal is between two fixed voltages. the ad8612 can be used to create a high speed window comparator, as shown in figure 26 . in this example, the reference window voltages are set as: 43 4 21 2 rr r v rr r v lo hi + = + = the output of the a1 comparator goes high when the input signal exceeds v hi , and the output of a2 goes high only when v in drops below v lo . when the input voltage is between v hi and v lo , both comparator outputs are low, turning off both q1 and q2, thus driving v out to a high state. if the input signal goes outside of the reference voltage window, v out goes low. to ensure a minimum of switching delay, the use of high speed transistors is recommended for q1 and q2. using the ad8612 with 2n3960 transistors provides a total propagation delay from v in to v out of less than 10 ns. table 8. window comparator output states v out input voltage 200 mv v in < v lo +5 v v lo < v in < v hi 200 mv v in > v hi v hi 5v 5v r1 r2 6 7 3 4 10 1 v in ad8612 1k ? v lo 5v r3 r4 9 8 11 5 12 14 ad8612 1k ? q1 5 v v out 1k ? 500 ? q2 500 ? notes 1. q1, q2 = 2n3960. 2. pins 2 and 13 are no connects. a1 a2 0 6010-023 figure 26. a high speed window comparator
ad8611/ad8612 rev. a | page 13 of 20 spice model * ad8611 spice macro-model typical values * 1/2000, ver. 1.0 * tam/adsc * * node assignments * non-inverting input * | inverting input * | | positive supply * | | | negative supply * | | | | latch * | | | | | dgnd * | | | | | | q * | | | | | | | qnot * | | | | | | | | .subckt ad8611 1 2 99 50 80 51 45 65 * * input stage * * q1 4 3 5 pix q2 6 2 5 pix ibias 99 5 800e-6 rc1 4 50 1e3 rc2 6 50 1e3 cl1 4 6 3e-13 cin 1 2 3e-12 vcm1 99 7 dc 1.9 d1 5 7 dx eos 3 1 poly(1) (31,98) 1e-3 1 * * reference voltages * eref 98 0 poly(2) (99,0) (50,0) 0 0.5 0.5 rref 98 0 100e3 *
ad8611/ad8612 rev. a | page 14 of 20 * cmrr = 66db, zero at 1 khz * ecm1 30 98 poly(2) (1,98) (2,98) 0 0.5 0.5 rcm1 30 31 10e3 rcm2 31 98 5 ccm1 30 31 15.9e-9 * * latch section * rx 80 51 100e3 e1 10 98 (4,6) 1 s1 10 11 (80,51) slatch1 r2 11 12 1 c3 12 98 5 4e-12 e2 13 98 (12,98) 1 r3 12 13 500 * * power supply section * gsy1 99 52 poly(1) (99,50) 4e-3 -2 6e-4 gsy2 52 50 poly(1) (99,50) 3 7e-3 -.6e-3 rsy 52 51 10 * * gain stage av = 250 fp=100 mhz * g2 98 20 (12,98) 0.25 r1 20 98 1000 c1 20 98 10e-13 e3 97 0 (99,0) 1 e4 52 0 (51,0) 1 v1 97 21 dc 0.8 v2 22 52 dc 0.8 d2 20 21 dx d3 22 20 dx * * q output *
ad8611/ad8612 rev. a | page 15 of 20 q3 99 41 46 nox q4 47 42 51 nox rb1 43 41 2000 rb2 40 42 2000 cb1 99 41 0.5e-12 cb2 42 51 1e-12 ro1 46 44 1 d4 44 45 dx ro2 47 45 500 eo1 97 43 (20,51) 1 eo2 40 51 (20,51) 1 * * q not output * q5 99 61 66 nox q6 67 62 51 nox rb3 63 61 2000 rb4 60 62 2000 cb3 99 61 0 5e-12 cb4 62 51 1e-12 ro3 66 64 1 d5 64 65 dx ro4 67 65 500 eo3 63 51 (20,51) 1 eo4 97 60 (20,51) 1 * * models * .model pix pnp(bf=100,is=1e-16) .model nox npn(bf=100,vaf=130,is=1e-14) .model dx d(is=1e-14) .model slatch1 vswitch(roff=1e6,ron=500, +voff=2.1,von=1.4) .ends ad8611
ad8611/ad8612 rev. a | page 16 of 20 outline dimensions compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 27. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa figure 28. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 coplanarity 0.10 compliant to jedec standards mo-153-ab-1 figure 29. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters
ad8611/ad8612 rev. a | page 17 of 20 ordering guide model temperature range package description package option branding ad8611arm-reel C40c to +85c 8-lead mini small outline package [msop] rm-8 g1a ad8611arm-r2 C40c to +85c 8-lead mini small outline package [msop] rm-8 g1a ad8611armz-reel 1 C40c to +85c 8-lead mini small outline package [msop] rm-8 g1a ad8611armz-r2 1 C40c to +85c 8-lead mini small outline package [msop] rm-8 g1a ad8611ar C40c to +85c 8-lead standard small outline package [soic_n] r-8 ad8611ar-reel C40c to +85c 8-lead standa rd small outline package [soic_n] r-8 ad8611ar-reel7 C40c to +85c 8-lead stan dard small outline package [soic_n] r-8 ad8611arz 1 C40c to +85c 8-lead standard small outline package [soic_n] r-8 ad8611arz-reel 1 C40c to +85c 8-lead standard small outline package [soic_n] r-8 ad8611arz-reel7 1 C40c to +85c 8-lead standard small outline package [soic_n] r-8 ad8612aru C40c to +85c 14-lead thin shrink small outline package [tssop] ru-14 ad8612aru-reel C40c to +85c 14-lead thin shrink small outline package [tssop] ru-14 ad8612aruz 1 C40c to +85c 14-lead thin shrink small outline package [tssop] ru-14 AD8612ARUZ-REEL 1 C40c to +85c 14-lead thin shrink small outline package [tssop] ru-14 1 z = pb-free part.
ad8611/ad8612 rev. a | page 18 of 20 notes
ad8611/ad8612 rev. a | page 19 of 20 notes
ad8611/ad8612 rev. a | page 20 of 20 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c06010-0-8/06(a)

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